Semiconductor integrated circuits have traditionally been packaged using wirebonding technology. In this technology, as illustrated in FIG. 1, a semiconductor die 10 is attached to a chip carrier 14 (of any of a number of different configurations, e.g., dual inline package) using an adhesive. The die 10 has a plurality of conductive wirebonding pads such as pad 18 arranged around the periphery of the die 10. These wirebonding pads 18 are connected to circuitry on the die 10 to make electrical connections such as power, ground and various signal connections, depending on the die's circuitry. In order to make these connections available outside of the die, pads such as 18 are electrically connected using fine wires such as 22 that are bonded to pads 18 and to corresponding wirebonding pads 28 on the chip carrier 14. The chip carrier 14 then provides interconnections to other circuitry by use of solder pins or pads connected to the chip carrier's pads such as 28.
Such wirebonding techniques have been used successfully for many years and remain in common use today. However, the above wirebonding technique has limitations in that the wirebonding pads must usually be arranged along the periphery of the semiconductor die. This limits the number of connections that can be made. Also, power and ground connections provided to circuitry located in a central area of the die may be a significant distance from the wirebond pad 18. As semiconductor processing technology improves, the conductors used to carry such power and ground connections can be extremely fine resulting in unacceptable impedance between the point of the wirebond and the circuitry being powered.
These problems are addressed in a solder bump die connection technology illustrated in FIG. 2. This technology, although originally pioneered in the 1960s, has been more widely adopted over the last several years. In this technology, solder pads are situated at any given location of a semiconductor die 38 and corresponding pads provided on a chip carrier or other substrate 44 to which the die is to be connected. Bumps of solder such as 46 are then screened onto the die 38 at the location of the die's solder pads through a mask that permits solder to only be deposited in the desired locations. The die 38 is then set into place on the substrate 44 aligning the solder pads of die 38 with those of substrate 44, and the assembly is heated to cause the solder to flow and create both a mechanical and electrical connection.
With this improved solder bump technology, much higher density can be achieved and the electrical interconnections can be made at virtually any location on the die's surface. However, as the density of circuitry provided on the die increases, an additional problem is encountered.
When the die contains circuitry made using a relatively low resolution process (e.g., greater than 0.09 micron line technology), and the die contains logic circuitry that can be selectively activated or deactivated (e.g., to provide redundancy, selective functionality or selective configuration), it is often sufficient to simply disable clocks to the circuitry that is to be disabled. However, as line resolutions get smaller, e.g., below 0.09 microns, the power consumption of the logic circuitry due to leakage currents may be a significant contribution to overall power consumption. Due to variations in the actual circuit configuration, of course, the above line sizes should be considered only exemplary of the potential problem.